LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;


entity extendunit is
  port ( 
    Imm         :   in std_logic_vector (15 downto 0);
    ExtOp         : in std_logic;
    Shift         : in std_logic;
    LoadUpper     : in std_logic;
    ImmExtend    :   out std_logic_vector (31 downto 0)
  );
end extendunit;

architecture arch of extendunit is
  signal shamt : std_logic_vector(4 downto 0);
  
  signal sel : std_logic_vector (1 downto 0);
  
  signal ImmExtend_1 : std_logic_vector(31 downto 0);
  
begin
  shamt <= Imm(10 downto 6);
  
  sel <= Shift & (ExtOp and Imm(15));
  
  with sel select
    ImmExtend_1 <= ("1111111111111111" & Imm) when "01",
              ("0000000000000000" & Imm) when "00",
              ("000000000000000000000000000" & shamt) when others;
              
  ImmExtend <= Imm & x"0000" when LoadUpper = '1' else
               ImmExtend_1;
  
end arch;